1. Field of the Invention
The present invention relates to a method for measuring parasitic components of a field effect transistor and to a semiconductor integrated circuit which can measure the parasitic components of a field effect transistor utilizing a pseudo field effect transistor.
2. Description of the Related Art
FIG. 3 is an equivalent circuit diagram showing one example of a field effect transistor model. For estimating the high-frequency operational characteristics of a field effect transistor or for simulating the operation of an electronic circuit using field effect transistors, it is necessary to have an accurate knowledge not only of the characteristics of a transistor's intrinsic region (labeled T and enclosed with a dotted line in FIG. 3) which relate to its operation, but also of its parasitic components. The characteristics of parasitic components are the characteristics attributable to the shape of transistor. Parasitic components include elements such as gate electrode Dg, source electrode Ds and drain electrode Dd; the shape of gate pad Pg, source pad Ps and drain pad Pd; lead-out electrodes for connecting electrodes Dg, Ds and Dd to either the outside or another electrode; and the shape of conductor patterns connecting electrodes to their respective pad.
In FIG. 3, Lg represents the gate inductance of a gate lead pattern (conductor pattern for connecting gate pad Pg to gate electrode Dg). Ld represents the drain inductance of a drain lead pattern (conductor pattern for connecting drain pad Pd to drain electrode Dd). Ls represents the source inductance of a source lead pattern (conductor pattern for connecting source pad Ps to source electrode Ds). Cgd, Cgs and Cds in the intrinsic region T represent the gate-drain capacitance, gate-source capacitance and drain-source capacitance, respectively. GmVi represents a current source for supplying the current corresponding to the mutual conductance gm and the gate input voltage Vi. Ri represents the gate input resistance and gd represents the drain conductance.
Various techniques have been proposed to enable more accurate measurement and estimation of the characteristics of a field effect transistor formed on the semiconductor substrate including that of its parasitic components. For example, a technique for measuring and estimating the characteristics of a field effect transistor by forming a pseudo pattern and installing a source test electrode to this pseudo pattern is disclosed in Japanese Patent Laid-Open Publication No. HEI 4-35542.
Another method which attempts to measure the gate resistance in a Schottky field effect transistor having a multi-layered electrode comprising two or more metal gate layers is disclosed in Japanese Patent Laid-Open Publication No. HEI 4-260349. This technique involves setting the forward flowing current in a Schottky contact region to a smaller value than that of the saturating current of the channel region and the resistance generated by a measuring current in the Schottky contact region to be small enough for the gate current.
There have also been attempts to eliminate the use of electrodes to estimate the characteristics of a field effect transistor because the use of a test electrode contributes to excess parasitic capacitance. Japanese Patent Laid-Open Publication No. HEI 3-232248, for example, attempts to eliminate the problem resulting from the influence of the test electrode by separating the measuring electrode by a distance smaller than the width of a probe away from the source electrode and allowing the measuring electrode to make a short circuit with the source electrode.
However, none of these methods allow accurate measurement of the parasitic components of a field effect transistor because they cannot isolate the parasitic components from the characteristics of the intrinsic transistor region.
It is therefore desirable to be able to isolate and accurately measure the parasitic components of a transistor because the shape of the parasitic components affects the high-frequency characteristics of the transistor. By improving the shape of electrodes and any other parasitic components, the characteristics of the transistor's intrinsic region can be used more effectively. Furthermore, by comparing the total characteristics of a field effect transistor (which includes both the intrinsic and parasitic components) with its parasitic components, the characteristics of the intrinsic region may be analyzed more accurately facilitating high-frequency circuit design.
It is accordingly an object of the present invention to provide a method for accurately measuring the parasitic components of a field effect transistor.
It is a further object of the present invention to provide a semiconductor integrated circuit with a pseudo field effect transistor for measuring the parasitic components of the field effect transistor.